New PDF release: A Designer’s Guide to Built-In Self-Test

By Charles E. Stroud

ISBN-10: 0306475049

ISBN-13: 9780306475047

ISBN-10: 1402070500

ISBN-13: 9781402070501

A contemporary technological improve is the paintings of designing circuits to check themselves, often called a integrated Self-Test (BIST). this concept was once first proposed round 1980 and has grown to develop into essentially the most vital checking out ideas on the present time, in addition to for the long run. This booklet is written from a designer's point of view and describes the foremost BIST methods which were proposed and applied given that 1980, in addition to their merits and boundaries. The BIST techniques contain the integrated common sense Block Observer, pseudo-exhaustive BIST concepts, round BIST, scan-based BIST, BIST for normal constructions, BIST for FPGAs and CPLDs, mixed-signal BIST, and the combination of BIST with concurrent fault detection suggestions for online trying out. specific realization is paid to system-level use of BIST for you to maximize some great benefits of BIST via decreased checking out time and price in addition to excessive diagnostic solution. the writer spent 15 years as a fashion designer at Bell Labs the place he designed over 20 creation VLSI units and three creation circuit forums. 16 of the VLSI units contained BIST of varied varieties for normal constructions and common sequential common sense, together with the 1st BIST for Random entry stories (RAMs), the 1st thoroughly self-testing built-in circuit, and the 1st BIST for mixed-signal structures at Bell Labs. He has spent the previous 10 years in academia the place his study and improvement maintains to target BIST, together with the 1st BIST for FPGAs and CPLDs besides persisted paintings within the sector of BIST for common sequential good judgment and mixed-signal platforms. He holds 10 US patents (with five extra pending) for numerous forms of BIST techniques. consequently, the writer brings a special combination of data and event to this functional consultant for designers, try out engineers, product engineers, process diagnosticians, and managers.

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3 it is evident that some of these faults behave identically and cannot be distinguished from each other as a result of their faulty behavior. For example, any stuck-at-0 input to an AND (NAND) gate is indistinguishable from the output of the gate being stuck-at-0 (stuck-at-1). These faults are equivalent faults and detecting any one of these faults is guaranteed to detect all of its equivalent faults [50]. As a result, Chapter 2. Fault Models, Detection, and Simulation 27 Chapter 2. Fault Models, Detection, and Simulation only one fault in each group of equivalent faults needs to be emulated; this helps to reduce fault simulation time by reducing the number of faults to be emulated.

Testing cost can sometimes be significantly reduced when BIST is incorporated into a VLSI device or PCB by eliminating the need for expensive external test machines [50]. The cost of these test machines is typically driven by the number of test vectors that must be stored, the speed at which the input test patterns must be applied and the output responses monitored, as well as the number of I/O pins that must be serviced. With BIST, the test patterns are produced internally by the TPG and the output responses are checked internally by the ORA.

Otherwise, a glitch on the output of the comparator could cause a fault-free CUT to appear faulty. Conversely, a glitch on the carry-out output of the counter could cause a faulty CUT to appear fault-free if the Pass/Fail result is read immediately after the BIST Done goes active and the glitch occurs prior to the completion of the BIST sequence and prior to the detection of the fault by the comparator. This type of BIST architecture is rarely used in practical applications since it requires conventional test vector development and considerable circuit area for the TPG and ORA ROMs as well as the counter.

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A Designer’s Guide to Built-In Self-Test by Charles E. Stroud

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