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The RDRF bit is cleared when the SCSR is read (with RDRF set) followed by a read of the SCDR. IDLE — Idle Line Detect The idle line detect bit, when set, indicates the receiver has detected an idle line. The IDLE bit is cleared by reading the SCSR with IDLE set followed by reading SCDR. Once the IDLE status flag is cleared, it will not be set again until after the RxD line has been active and becomes idle again. OR — Overrun Error The overrun error bit is set when the next byte is ready to be transferred from the receive shift register to the SCDR which is already full (RDRF bit is set).

Bit 0 — Not Implemented This bit always reads zero. 5 Baud Rate Register (BAUD) The baud rate register selects the different baud rates which may be used as the rate control for the transmitter and receiver. The SCP[0:1] bits function as a prescaler for the SCR[0:2] bits. Together, these five bits provide multiple baud rate combinations for a given crystal frequency. $102B RESET 7 TCLR 0 6 0 0 5 SCP1 0 4 SCP0 0 3 RCKB 0 2 SCR2 U 1 SCR1 U 0 SCR0 U BAUD TCLR — Clear Baud Rate Counters (Test) This bit is used to clear the baud rate counter chain during factory testing.

When full input handshake protocol is specified, both general purpose input and/or general purpose output can coexist at port C. When full output handshake protocol is specified, general purpose output can coexist with the handshake outputs at port C, but the three-state feature of the output handshake mode interferes with general purpose input in two ways. First, in full output handshake, the port C lines are outputs whenever STRA is at its active level regardless of the data direction register bits.

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68HC11 Technical Docs


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